Anders Nordstrom is a senior corporate applications engineer in Synopsys’ Verification Group working on formal methodology and features on the VC Formal tool. He has 20 years’ experience in assertion-based verification and formal property verification, in EDA and as a verification engineer. This analysis allows Questa Formal Verification to explore the whole state space in a breadth-first manner, in contrast to the depth-first approach used in simulation. Questa Formal Verification is therefore able to discover any design errors that can occur, without needing specific stimulus to.
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Hello,I have a SystemVerilog module containing concurrent assertions for formal property verification that is bound to a VHDL design under verification.I wanted to use some Verilog code in this module to support my assertions. I tried 2 different versions of always blocks. The one using $rose allows the cover property to be coverable. The one using posedge makes the cover property uncoverable.There are no assumptions, no other assertions or cover properties. TestSignal is connected to a input of the VHDL block. EtCount is a dummy int variable.default disable iff(rst);default clocking c0 @(posedge clk); endclockinginitial beginetCount = 0;endcover property (##0:$$rose(testSignal));// with this block the cover property is coverablealways @($rose(testSignal)) beginetCount.
// Correct way always @ ( posedge clk ) begin if ($rose (testSignal ) ) begin - eclk; # 2 etCountclk. In reply to:Dear Ben,thank you for your example and explanation.Can you please explain me why erose is generated two times each time the testSignal rose?
When the clocking event is specified to @(posedge clk), I would have expected that it only happens at the positive clock edge, not at the positive edge of testSignal.I put this code into a module for formal verification. I was actually surprised that I can use $rose outside a property, because I thought the always blocks would be synthesized. I am not sure how $rose is behaving in synthesized code.And then I am wondering how using the signal in an always block can have an influence on the coverability of the cover property. Do you know that?Thank you,K.
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